SANTA CLARA, CALIF. — December 11, 2000 — Sequence Design Inc., the specialist provider of power and timing-closure software for system-on-chip design, today announced Transmeta Corporation will use Sequence’s Watt Watcher™ power analysis and optimization products in the design of advanced low-power microprocessor chips for portable applications, where battery life is a critical concern.

The Sequence tools will be used to help explore the impact of different architecture and logic design choices on chip power requirements. Transmeta chose the Sequence tool set based on its ability to assess chip power requirements accurately at the register-transfer level (RTL), a very early stage in the chip development process.

"Architectural choices are really what determine chip power, and innovative processor architecture has been at the core of Transmeta’s ability to deliver high performance but low-power computing platforms," said Fergus Slorach, EDA manager, Transmeta Corporation. "Adding the Sequence tools to our design methodology is one of a number of steps we’re taking to ensure the Crusoe architecture continues to set the industry’s benchmark for power efficiency, while enabling the longest possible battery life for our OEM customers."

"Transmeta has become synonymous with achievement and innovation in low power design," said Eric Filseth, vice president, product marketing for Sequence. "The mobile internet market demands extended battery life while delivering high computing performance and sophisticated functionality. We’re extremely pleased to be able to participate in this initiative."

About Watt Watcher™

The Watt Watcher product family is the de facto standard for RTL (register transfer level) and gate-level power analysis and optimization in system-on-chip integrated circuits. Watt Watcher’s fast throughput, full-chip capacity, and unique architecture-level approach help design teams reduce power in advanced silicon for broadband networking, wireless communications, complex ASIC, low power designs and other demanding applications.

Cool-by-Design Methodology

In system-on-chip development, the overwhelming majority of a chip’s power behavior is determined in the early stages of design, and prior to logic synthesis. In a Cool-by-Design methodology, chip power requirements are assessed as early as possible in development — normally at RTL, where accurate power data first becomes available. Any necessary power optimization is then performed immediately, while significant impact can still be made; detailed power verification is performed in subsequent design stages. The result is a manageable, predictable power design methodology which produces more power-efficient IC’s while avoiding "surprise" problems not detected until the end of the design cycle.

About Sequence

Sequence Design Inc. is the premier provider of power and timing optimization for design closure in system-on-chip integrated circuits. Sequence’s chip design software and services enable engineering teams to develop superior products quickly, in order to achieve competitive advantage in high-growth technology markets. Customers include Broadcom, Ericsson, Fujitsu, LSI Logic, NEC, Nokia, Nortel Networks, MMC Networks, Sony, Sun Microsystems, Texas Instruments, Toshiba and Vitesse Semiconductor.

Sequence supports worldwide development and field service operations. The company was formed through the merger of Sente, Inc and Frequency Technology. Sequence is privately held; investors include IVP, Menlo Ventures, Alpine Technology Ventures, Atlas Venture, Intel, Sumitomo Corporation, LSI Logic, Sofinnova, Skywood Ventures and Sigma Partners.

Sequence is a member of Cadence Design Systems’ (NYSE: CDN) Connections™ and Mentor Graphics’ (NASDAQ: MENT) Open Door™ partnership programs. Please visit our web site at www.sequencedesign.com.

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